Field programmable digital signal processing array integrated circuit

ABSTRACT

A field programmable, digital signal processing integrated circuit is formed in a semiconductor die and includes an array of arithmetic logic (ALU) circuits. A user programmable interconnect architecture is superimposed on the array of ALU circuits. One or more interface circuits comprising digital-to-analog (D/A) converters or analog-to-digital (A/D) converters are  may be provided on the integrated circuit to interface to off-chip analog input signals and provide off-chip analog output signals. Circuitry is provided to program the interconnections between the interface circuits and the ALU circuits and between individual ones of the ALU circuits, as well as to define the specific functions of the individual ALU circuits.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to integrated circuits and, morespecifically, to user-programmable integrated circuits. Moreparticularly, the present invention relates to user-programmable mixedanalog and digital integrated circuits.

2. The Prior Art

General purpose linear integrated circuits have limited themselves tospecific functions such as operational amplifiers, phase locked loops,comparators, A/D converters, video amplifiers, transistor arrays, etc.These circuits form the building blocks of analog systems. Integratingthese circuits into higher functions is difficult due to the need toemploy external components (i.e., resistors, capacitors, inductors,etc.) to determine their exact function. Thus once integrated, thesecircuits become specialized. In order to be practicable for design,manufacture, and sale, such a specialized part must have a large usagebase. One illustrative example of such a circuit is an audio amplifierwhich may be used in stereo systems or television sets. Without a largeusage base, the design and manufacture of such a circuit is noteconomical.

During the manufacture of analog circuits a significant cost is thefinal trimming of each individual circuit. This is required becauseactual component values vary as well as stray capacitance is introduceddue to component placement.

Another common problem in electronics is that various parts of a complexsignal need to be kept in phase while utilizing different circuit paths.This For example, this is commonly done in color television sets wherethe luminance information is routed through a delay line while thechrominance information is processed.

Furthermore, many common analog systems such as television sets, VCR'sVCRs and stereo systems are currently employing many digital functions.Hence the integration of these circuits onto a single integrated circuitdie requires mixed analog and digital design and a process tomanufacture them such integrated circuits. The manufacturing process forsuch integrated circuits is complex and expensive as the transistorsused in analog circuit design are typically radically different fromthose used in digital design.

One prior-art prior art approach to this problem has been to designcircuits which operate employing digital signal processing (DSP)techniques. These devices use Such circuits employ a microprocessor coreto simulate the mathematical equivalent of the analog system. One commonapplication for such chips circuits is digital filtering of thedigitized analog signals before conversion of such signals back to theanalog world .

A fundamental limitation of these integrated DSP devices is that thedevice speed is limited by the Von Neuman architecture of themicroprocessor where many processor functions are required for each timeslice of the analog signal. This limitation has heretofore limited thespeed of such devices to frequencies in the audio spectrum. This is ofcourse due to the fact that the customization of the function isachieved by the coding of the instructions in the microprocessor.

Another approach to the mixed analog and digital integrated circuit isshown in U.S. Pat. No. 5,107,146 to El-Ayat. This patent discloses auser-programmable architecture including a mixture of analog and digitalcircuit modules. The digital logic modules are of the type used in priorfield programmable gate array (FPGA) devices.

Work has been done in the past in trying to design processor arrays tospeed up applications. These This class of machines are is called MIMDor SIMD (multiple instruction multiple data or single instructionmultiple data). These concepts utilize a plurality of processor enginesto perform logical operations, such as multiplication and division. Eachprocessor engine is a Von Neuman machine and occupies significant diearea on an integrated circuit.

It is an object of the present invention to provide a user-programmabledigital signal processing integrated circuit which overcomes thelimitations of the prior art.

It is another object of the present invention to provide auser-programmable digital signal processing integrated circuit whichdoes not require individual component trimming to maximize performance.

Yet another object of the present invention is to provide auser-programmable digital signal processing integrated circuit whichallows the user to control phase shifting of signals being processedtherein.

It is a further object of the present invention to provide auser-programmable digital signal processing integrated circuit which maybe easily programmed by a user.

BRIEF DESCRIPTION OF THE INVENTION

According to the present invention, a field programmable, digital signalprocessing integrated circuit is formed in a semiconductor die andincludes an array of arithmetic logic unit (ALU) circuits. A userprogrammable interconnect architecture is superimposed on the array ofALU circuits. One or more interface circuits comprisingdigital-to-analog (D/A) converters or analog-to-digital (A/D) convertersare provided on (or off) the integrated circuit to interface to off-chipanalog input signals and provide off-chip analog output signals. Otherfunctional circuit blocks, such as programmable read only memory (PROM)or Random Access Memory (RAM) circuits may also be disposed on theintegrated circuit die. Circuitry is provided to program theinterconnections between the interface circuits and the ALU circuits andbetween individual ones of the ALU circuits, as well as to define thespecific functions of the individual ALU circuits.

The architecture of the present invention avoids the Von Neuman bottleneck characteristic of prior art systems by eliminating the need forsequential instructions. Each ALU circuit of the present invention maybe user customized to act like the mathematical equivalent of an analogcircuit element. The individual ALU circuits are interconnected to oneanother and to A/D and D/A interface circuits by user-programmableinterconnect elements.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of the architecture for an illustrative fieldprogrammable digital signal processing integrated circuit according to apreferred embodiment of the present invention.

FIG. 2a 2A is a block diagram of an illustrative ALU circuit suitablefor inclusion in the field programmable digital signal processingintegrated circuit according to the present invention.

FIG. 2b 2B is a state diagram which discloses in detail the operation ofthe control circuit portion of the ALU circuit of FIG. 2a 2A.

FIG. 3 is a schematic diagram of an architecture for a bus interchangewhich can perform a single or multibit shift operation.

FIG. 4a 4A is a schematic diagram of a simple inverting analogamplifier.

FIG. 4b 4B is an equivalent block diagram of the amplifier of FIG. 4a 4Aimplemented according to the present invention.

FIG. 4c 4C is an equivalent block diagram of the amplifier of FIG. 4a 4Aimplemented according to the present invention and including alogarithmic feedback element.

FIG. 5 is a graph showing the waveforms of the signal input and signaloutput waveform of the circuit of FIG. 4b 4B for a sinusoidal inputwaveform.

FIG. 6 is a graph showing the waveforms of the signal input and signaloutput waveform of the circuit of FIG. 4b 4B for a square inputwaveform.

FIG. 7a 7A is a schematic diagram of a variation of the amplifiercircuit of FIG. 4a 4A.

FIG. 7b 7B is an equivalent block diagram of the amplifier of FIG. 7a 7Aimplemented according to the present invention in a manner which avoidspipelining distortion in the output.

FIG. 8 is a graph showing the input and output voltages of the circuitof FIG. 7b 7B for 1 MHz sine wave input.

FIG. 9 is a graph showing the input and output voltages of the circuitof FIG. 7b 7B for 1 MHz square wave input.

FIG. 10 is a block diagram of an illustrative analog shift registerconfigured using the architecture of the present invention.

FIGS. 11a 11A and 11b 11B are examples of a series RLC tuned circuitimplemented according to the present invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

Those of ordinary skill in the art will realize that the followingdescription of the present invention is illustrative only and not in anyway limiting, Other embodiments of the invention will readily suggestthemselves to such skilled persons.

Referring first to FIG. 1, a block diagram is presented of thearchitecture for an illustrative field programmable digital signalprocessing integrated circuit according to a preferred embodiment of thepresent invention. The architecture of the present invention isintegrated on a single piece of semiconductor material, and may befabricated using known semiconductor processing technology, such as CMOStechnology, which is presently preferred.

The field programmable digital signal processing integrated circuit 10of the present invention is built around an array of arithmetic logicunit (ALU) circuits shown at reference numerals 12-1 through 12-9. Forpurposes of illustration, arithmetic logic units 12-1 through 12-9 areshown arranged as a regular array comprising three rows and threecolumns of ALU circuits. Those of ordinary skill in the art will readilyobserve that the architecture and arrangement of FIG. 1 is illustrativeonly and not limiting, in that such skilled persons will readilyrecognize that other numbers of ALU circuits and other layoutarrangements may be employed.

At least one analog-to-digital (A/D) converter and at least onedigital-to-analog (D/A) converter circuit may be optionally disposed onthe integrated circuit along with the ALU circuits. In the illustrativeembodiment of FIG. 1, two A/D circuits 14-1 and 14-2 and two D/Acircuits 16-1 and 16-2 are shown. In an actual embodiment of theintegrated architecture of the present invention, A/D converters 14-1and 14-2 and D/A converters 16-1 and 16-2 will probably be located nearthe periphery of the integrated circuit die upon which the architecture10 of the present invention is disposed, but those of ordinary skill inthe art will understand that placement of these devices is largely amatter of design choice. Such elements may even be located off chip incertain applications.

As in any integrated circuit, a plurality of input/output (I/O) pins areprovided for supplying power to the integrated circuit and fortransporting electrical signals onto and off of the integrated circuit.The number of I/O pins provided on any actual embodiment of thearchitecture of the present invention will be purely a matter of designchoice. A group of such I/O pins is depicted as a single I/O block 18,but those of ordinary skill in the art will recognize that I/O block 18represents a plurality of I/O pins.

Other functional circuit blocks may be disposed in the integratedcircuit along with the other previously-described elements. For example,and as shown in FIG. 1, PROM devices 20-1 and 20-2 are shown disposed inthe integrated circuit architecture 10 of the present invention. Thoseof ordinary skill in the art will realize that other types of circuitelements, such as RAM and ROM circuits, may be usefully employed in thearchitecture of the present invention.

Finally, a user-programmable interconnect architecture is superimposedupon the aforementioned circuit elements. The user-programmableinterconnect architecture is used to connect the aforementioned circuitelements to one another and to the I/O pins.

User-programmable interconnect architectures include a plurality ofinterconnect conductors which may be connected to one another, to inputsand outputs of the various circuit elements, and to the I/O pins byuser-programmable interconnect elements. These user-programmableinterconnect elements may take several forms as is known in the art.Examples of such elements include antifuses, of which there are numerousknown examples, such as those disclosed in U.S. Pat. Nos. 4,899,205, and5,070,384, and 5,181,096, and pass transistors, such as disclosed in thearchitecture described in U.S. Pat. No. 4,870,302. Those of ordinaryskill in the art will recognize that these examples are non-exhaustiveand merely illustrate the state of the user-programmable interconnectelement art. Unless specifically noted otherwise herein, the meaning ofthe term user-programmable interconnect element as used herein shall beconstrued to cover all forms of such interconnect elements. Thestructure, design, and use of such user-programmable interconnectelements is well known in the art and will not be recited herein.

In FIG. 1, the user-programmable interconnect architecture is showndiagrammatically as horizontal interconnect conductors 22 and verticalinterconnect conductors 24 which are distributed throughout and amongthe circuit elements of FIG. 1. Those of ordinary skill in the art willrecognize that FIG. 1 is very general in this respect. The linesidentified by reference numerals 22 and 24 in the drawing figure are notintended to represent individual interconnect conductors but ratherrepresent groups of conductors. An actual arrangement of interconnectconductors useful for employment in the present invention will bedisclosed in subsequent figures and text herein.

In actual embodiments of the architecture of the present invention, someof the conductors will be segmented and some conductors may run theentire length or width of the array of circuit elements in thearchitecture. Individual user programmable interconnect elements will beconnected between selected adjacent segments of the interconnectconductors to selectively lengthen them, and other individualuser-programmable interconnect elements will be positioned betweenintersecting horizontal and vertical segments of the interconnectconductors. Nonexhaustive examples of the segmenting of individualinterconnect conductors are seen in U.S. Pat. Nos. 4,870,302, 4,758,745,and 5,073,729.

Those of ordinary skill in the art will understand that care must betaken in the design of the segmentation of the interconnect conductors.Normally, output signals from an ALU circuit will be passed to a nearestneighbor ALU immediately above, below, or to either side. However, somecircuits (such as reactive circuits) need to feed the terms back veryquickly, making short busses necessary. In addition, a signal mustoccasionally be fed a long distance as is the case of for an AGC(automatic gain control) signal. Long buses will be needed to be usedfor these signals. Fortunately these are often slow responding signalsand will not limit the circuit speed. Those of ordinary skill in the artwill understand that it is preferable that as few user-programmableinterconnect elements as possible should be interposed in a singlesignal path to minimize signal delay.

Although, in a normal circuit configuration defined by a user, most ofthe interconnect conductors comprising the interconnect architecture areshown on the digital side of the circuit, i.e., between the outputs ofA/D converters 14-1 and 14-2 and the inputs of D/A converters 16-1 and16-2, there are situations where it becomes advantageous to have accessto the internal interconnect conductor groups from outside of theintegrated circuit. According to one aspect of the present invention,the interconnect conductor groups may communicate with the I/O pins,either directly, as shown in FIG. 1 by leftmost and rightmost verticalinterconnect conductor groups 24 entering I/O block 18, or throughappropriate input and output buffers as is known in the art. Thisfeature of the present invention allows a number of integrated circuitsaccording to the present invention to be connected together to formlarger circuits, which may be clocked together as will be describedfurther herein.

Referring now to FIG. 2a 2A, the structure and organization of apresently preferred single ALU circuit 12 suitable for use in thearchitecture of the present invention is depicted in block diagram form.ALU circuit 12 may be configured using standard CMOS building blocks forcircuits of this type. Those of ordinary skill in the art will recognizethat other ALU circuits and variations of the circuit presented in FIG.2a 2A are useable in the present invention.

According to a presently preferred embodiment of the present invention,ALU circuit 12 includes an a first 2:1 multiplexer 26 and a second 2:1multiplexer 28. Both the first and second multiplexers 26 and 28 aren-bits wide, where n is the width of the data byte used by the ALUcircuit 12. The byte size used in any actual embodiment of the inventioncould be from 2-64 bits wide and will be dictated by resolution, size,and other design considerations. A typical byte size might be, forexample, 8 bits. Practically a data byte would be the width of the A/Dand D/A converters used. This would be for instance 8 or 10 bits in thecase of Video D/A converters and 18 bits for Audio D/A converters.

For some applications however, variations on this structure may benecessary. For example, the voltage in tuned reactive circuits is Q(quality factor) times higher than the input voltage. Typically a Q maybe as high as 100, which would require an extra 8 bits to be added tothe ALU circuits 12 to accommodate the voltage, resulting in 16 to 18bits for Video D/A converters. If the programmable circuit is optimizedfor reactive circuits, only the internal nodes of the reactive circuitsneed be this size. The rest of the ALU circuit 12 data paths could be 8to 10 bits wide. Another solution to this problem would be to configureall of the ALU circuits 12 to be 8 to 10 bits wide and to program an AGCcircuit consisting of a peak detector, a comparator and gain adjustcircuit into the circuit to reduce the input signal amplitude to thereactive circuit module, thereby preventing the ALU circuit 12 fromoverflowing. Those of ordinary skill in the art will envision numerousother similar modifications of the basic architecture of the presentinvention.

Referring again to FIG. 2a 2A, the data inputs (A and B) of first 2:1multiplexer 26 are connected to n-wide input busses 34 and 36, and thedata inputs (C and D) of second 2:1 multiplexer 28 are connected ton-wide input busses 32 and 34. Numerous other configurations arepossible, but it is preferred that the input busses physically exit theALU circuit 12 in different directions to maximize the interconnectpossibilities. For example, one end of input busses 30, 32, 34, and 36might exit the ALU block horizontally and one end may exit vertically topermit connection to both horizontal and vertical interconnectconductors in the interconnect matrix of the integrated circuit, thusallowing for greater interconnect possibilities. This is showndiagrammatically in FIG. 1 in the region of ALU circuit 12-1 atreference numerals 30a, 32a, and 34a. While only one ALU circuit 12-1 isshown having such an input structure in FIG. 1, in order to avoidcluttering up the drawing, those of ordinary skill in the art willrecognize that it is preferable for all ALU circuits to be similarlyconfigured.

The control inputs 38 and 40 of first and second 2:1 multiplexers 26 and28 are brought to an interconnect matrix which includes conductor 42carrying the Vcc potential for the integrated circuit, conductor 44carrying ground potential, and general interconnect conductors 46, 48,and 50. The small circles in the interconnect matrix at theintersections of control inputs 38 and 40 and conductors 42, 44, 46, 48,and 50 represent user programmable interconnect elements, such asantifuses or pass transistors. Those of ordinary skill in the art willrealize that the arrangement shown allows maximum flexibility in thatthe control inputs 38 and 40 of the multiplexers 26 and 28 can behardwired to Vcc or ground to preselect the data source or can behardwired to data sources via one of general interconnect conductors 46,48, or 50 to dynamically alter the signal sources during circuitoperation.

Those of ordinary skill in the art will recognizer recognize that themultiplexed inputs of the ALU circuit circuits 12 permit greaterinterconnect flexibility. Such persons will also recognize that, in someapplications, these circuit elements will not be necessary.

The outputs of first and second 2:1 multiplexers 26 and 28 are directedto negate circuits 52 and 54. The function of negate circuits 52 and 54is to selectively invert the data state of the input, and the circuitsmay be configured from exclusive OR gates as is known in the art. Thecontrol inputs 56 and 58 of negate circuits 52 and 54 are brought intothe interconnect matrix, thus allowing maximum flexibility of the negatefunction.

The outputs of negate circuits 52 and 54 drive the Latch A latches 60and 62. The outputs of Latch A latches 60 and 62 form the input termsfor adder 64. Adder 64 may be a conventional multibit adder circuit. Theoutput of adder 64 drives the input of Latch B latch 66. The output ofLatch B latch 66 is connected to output bus 68.

The Latch A latches 60 and 62 and Latch B latch 66 are controlled by acontrol circuit 70. The purpose of control circuit 70 is to synchronizethe operation of the ALU circuit to assure that the operation of thecircuit is coordinated with the arrival of the correct data to beprocessed by the ALU circuit. Control circuit 70 has a clock (CLK) input72, an enable (EN) input 74 and an input-ready in (INRIN) input 76.These inputs are incorporated into an interconnect matrix including twoclock lines CLKA line 78, CLKB line 80, and three general interconnectconductors 82, 84, and 86. The input lines 72, 74 and 76 are connectableto any of lines 78, 80, 82, 84 and 86 by the user programmableinterconnect elements shown as small circles at the intersections of thelines 78, 80, 82, 84 and 86 and the input lines 72, 74 and 76. Those ofordinary skill in the art will recognize that the connectivity choicesshown in FIG. 2a 2A are only illustrative, and that the actual choicesin an architecture built in accordance with the teachings of the presentinvention will be dictated largely as a matter of design choice.

Control circuit 70 has four outputs. Output A (line 88) drives theclocks of the Latch A Latches 60 and 62, and output B (line 90) drivesthe clock of the Latch B latch 66. INROUT line 92 is used forasynchronous connection of modules and is an input-read output signalwhich would be connected to the input-read (INRIN) input of the moduleconnected upstream so that the upstream module will release data on thenext clock. DATARDY line 94 is a data ready output used to indicate thatdata is valid for the next module downstream to read.

Those of ordinary skill in the art will recognize that, by using thenegate circuits 52 and 54 and the multiplexers 26 and 28, the ALUcircuit 12 of FIG. 2a 2A may be configured to perform the customarylogical functions performed by ALU circuits.

Referring now to FIG. 2b 2B, a state diagram is presented, showing indetail the operation of the control circuit 12 portion of the ALUcircuit of FIG. 2a 2A. Those of ordinary skill in the art will recognizethat synchronous stages will not need to utilize the INRIN and INROUTlines 76 and 92. Asynchronous stages, however, will use the INRIN andINROUT lines 76 and 92 at the interface. Occasional bytes may be lost,but this should not affect the overall operation of any circuitsconfigured using the architecture of the present invention. Lost bytesmay be averaged out by (A+B)/2 of subsequent data bytes until smoothnesslevel is achieved, so long as the number of data samples per cycle areis adequate.

Those of ordinary skill in the art will recognize that variations of thearchitecture of the ALU module 12 of the present invention are possibleand are intended to fall within the scope of the present invention. Forexample, internal memory could be provided in the ALU modules 12 forinstructing them to perform more than one function and thus increasetheir flexibility. However, such skilled persons will recognize that, inits limit, such an embodiment will suffer from the Von Neuman bottleneckproblem of prior art architectures.

The organization of the interconnect architecture of the presentinvention makes it possible to utilize the interconnect itself toperform mathematical functions such as multiply and divide. This featureof the present invention is advantageous in that such operations may beperformed in the same clock cycle as the operations performed by the ALUcircuit whose output is driving the interconnect conductors.

The speed will be limited by the rate at which the ALU circuits canperform an addition (subtraction) and a multiplication (division). Themultiplication and division are the mathematical processes that take themost time. If, however, the application circuit is designed to usecircuit elements such as resistors, capacitors, inductors etc. in unitsof the power of 2, i.e., 2, 4, 8, 16, etc., the multiplication anddivision may be digitally represented by a shift left or a shift rightoperation.

As previously mentioned, these shifts can be built into the interconnectarchitecture. An exemplary scheme for performing such an operation isshown in FIG. 3. FIG. 3 shows a plurality of horizontal interconnectconductors 22-1 through 22-6 intersecting a plurality of verticalinterconnect conductors 24-1 through 24-6. At each intersection, atransistor 96-1 through 96-36 is connected between the horizontal andvertical interconnect conductors. The gates of diagonally-situated onesof the transistors are connected together to one of gate lines 98-1through 98-11

Those of ordinary skill in the art will appreciate that transfer of datafrom conductors 22-1 through 22-6 to corresponding ones of 24-1 to 24-6will take place when gate line 98-6 is activated. Data can be shiftedone bit in a first direction in the transfer if gate line 98-5 isactivated, two bits if gate line 98-4 is activated, three bits if gateline 98-3 is activated, and so on. Similar shifting will take place aselected number of bits in the other direction if one of gate lines 98-7through 98-11 is selected.

Those of ordinary skill in the art will recognize that this bit shiftingtechnique can be implemented by other user-programmable interconnectdevices such as antifuses. In such an embodiment, intersectingconductive lines may be connected by antifuses and the bit shifting tothe left or right may be accomplished by selective programming of theantifuses.

A bus interchange like that depicted in FIG. 3 may be placed at theintersection of horizontal and vertical interconnect conductors such as22 and 24 and may also be employed to connect an input bus or an outputbus of an ALU circuit to the horizontal and vertical interconnect bussesof the interconnect architecture. It is apparent that the multiplicationand division operations implemented by the shift function disclosedherein will take no significant time, and will certainly occur in thesame clock cycle used to operate the driving ALU circuit. Hence those ofordinary skill in the art will appreciate that the architecture of thepresent invention can perform functions with the same approximate speedas high speed analog operational amplifiers.

As an example of the use of this technique, an ALU circuit functioningas a digital resistor receives two multibit digital values representingthe voltages across its terminals and outputs a multibit digital valuerepresenting the current through it by the function I=(V_(A)−V_(B))/R,where R represents its resistance. The value of R as any power of 2 maybe preprogrammed into the ALU circuit by shifting the output bus one ormore bit positions. This function could be achieved in one clock cycleand the digital resistor performs the same function on each clock cycle,i.e. subtract two input numbers and divide by a preprogrammed constant.Hence the architecture of the present invention eliminates the need forprogram storage. Similarly a capacitor would be V=Vo+(I/C), where theinputs are currents and the output is a voltage. The division operationfor calculating capacitances whose values are powers of 2 isautomatically performed as a result of a bit shift of one or more placesin the opposite direction from that for a multiplication operation.Similar simple functions exist for inductors and transformers andoperational amplifiers, comparators, ideal diodes, switches ormultiplexers, which are the building blocks of analog electronics.

In an integrated circuit of the present invention, the user-programmedinterconnect of the digital ALU circuits would be a one-to-one map ofthe analog equivalent. The additional integration of digital signals issimple because the digital gates would be made of the same type oftransistors for digital circuits. The digital modules may use similarlogic as is currently available in Gate arrays, FPGA's FPGAs and PAL'sPALs. The interconnection of the analog elements may of course be madein the same manner as used in Gate arrays, FPGA's FPGAs and PAL's PALs.

An integrated circuit according to the present invention is easilycustomizable, suitable for mixing analog and digital functions, and canbe extremely fast, capable of working with analog signals in the RF andVideo frequency ranges. The limiting frequency will likely be the rateof A/D and D/A conversions at the boundaries of the system. Flashconverters currently work in the tens of megahertz. The A/D and D/Aconverters could either be on chip or off chip depending on the desireof the designed/manufacturer.

Referring now to FIGS. 4a 4A and 4b 4B, a simple design of an invertingunity gain amplifier is shown as an example of the operation of thearchitecture of the present invention. FIG. 4a 4A is a schematic diagramof the analog equivalent circuit including two one ohm resistors, a 40nF capacitor, and an amplifier having a slew rate of 0.25 V/V_(IN). FIG.4b 4B is a block diagram of the digital equivalent circuit asimplemented in the architecture of the present invention. An analoginput voltage is supplied to A/D converter 100, which presents itsoutput to ALU 102, programmed to behave as the resistor R1 in thecircuit of FIG. 4a 4A. ALU 104 is programmed to behave as capacitor C,ALU 106 is programmed to behave as resistor R2, and ALU 108 isprogrammed to behave as the amplifier element. The entire circuit isdriven by a 100 MHz clock 110. ALU 102 (resistor 1R1) computes the valueI₁=(V_(IN)−V₁)/1 Ω. ALU 104 (capacitor C) computes the valueV₁=V_(1prev)+(I₁+I₂)(10 nsec/40 nF), where V_(1prev) is the voltage fromthe previous clock cycle and 10 nsec is the period of the clock signal.ALU 106 (resistor 2R2) computes the value I₂=(V_(OUT)−V₁)/1 Ω. Finally,ALU 108 (the amplifier) computes the valueV_(OUT)=(V_(OUTprev)+(−0.25)V₁).

If one or (if necessary) both of the PROM elements 20-1 or 20-2 are usedin place of the feedback loop of the amplifier, special non-lineartransforms, such as logarithmic output of the amplifier, can beimplemented. The data stored at each address is simply the log of theaddress value. Such a variation of the amplifier circuit is shown atFIG. 4c 4C. Those of ordinary skill in the art will recognize that thelog function generator 114 may be implemented by use of a ROM look-uptable.

FIG. 5 is a graph showing the waveforms of the signal input and signaloutput waveform of the circuit for a sinusoidal input waveform. It maybe seen from FIG. 5 that the output of the amplifier is somewhat “phaseshifted” due to the pipelining time for the data through the ALU systemwhich emulates the analog amplifier.

FIG. 6 is a graph showing the waveforms of the signal input and signaloutput waveform of the circuit of FIG. 4b 4B for a square inputwaveform. The damped overshoot characteristic which is typical of analogamplifiers may be seen on the output waveform.

According to another aspect of the present invention, re-arranging thearchitecture of the emulated amplifier circuit can eliminate thedistortion exhibited by the circuit of FIG. 4b 4B which is apparent inFIGS. 5 and 6. Referring now to FIGS. 7a 7A and 7b 7B, an alternateconfiguration can be configured by employing a slower master clock andusing the data-valid (INR and OUTR) connections of the ALU circuits. Forconvenience, the same reference numerals are used in the circuits ofFIGS. 4b 4B and 7b 7B, but the capacitor C has a value of 60 nF and theamplifier has a gain of 2.

In the circuit of FIG. 7b 7B, the calculations in the R1 and R2 ALUcircuits (reference numerals 102 and 106) are performed first.Specifically, R1 ALU calculates I_(I)=(V_(IN)−V₁)/1 Ω. and R2 ALUcalculates I₂=(V_(OUT)−V₁)/1 Ω. The C ALU (reference numeral 104)calculates V₁=V_(1prev)+(I₁+I₂)(30 nsec/60 nF). This ALU is not clockeduntil the OUTR outputs of R1 and R2 ALU circuits 102 and 106 are true,indicating that the data at their outputs is valid. The AMP amplifierALU 108 calculates the value V_(OUT)=V_(OUTprev)−2V₁ and is not clockeduntil the OUTR output of ALU circuit 104 is true.

FIGS. 8 and 9 are graphs showing the input and output voltages of thecircuit of FIG. 7b 7B for 1 MHz sine and square wave inputs,respectively. Those of ordinary skill in the art will recognize that,while the phase of the output voltages are lagging the input voltages,the square wave output is completely free of overshoot. Such skilledpersons will also recognize that, due to the slower clocking speed(i.e., 33 MHz as opposed to 100 MHz for the circuit of FIG. 4b 4B),fewer data points are used to define the output function.

Another common problem encountered in analog electronics is that variousparts of a complex signal must often be kept in phase while utilizingdifferent circuit paths. A typical example of such a situation is incolor television where the luminance information is routed through adelay line while the chrominance information is processed.

The architecture of the present invention may be used to implement ananalog shift register as shown in FIG. 10, thus making possible anylength delay without phase alteration. In the example of FIG. 10, threeALU modules 120, 122 and 124 are shown connected as an analog shiftregister. The ALU modules are configured to compute the function(V1+0)/1, by connecting the B input busses of each to ground and the Ainput busses of each module to the output bus of the preceding ALUmodule in the chain. This technique may be used to configure an analogshift register chain of arbitrary length, although only three stages areshown in FIG. 10.

The present invention may also be employed to simulate tuned circuits.Tuned circuits have to be designed with a specific frequency orcontinuum of frequencies, not just a factor of a square root of two(f=½πsqrtLC), as would be the case were where L and C are limited tovalues equal to powers of 2. In digitally emulated tuned circuitsaccording to the present invention, the actual value of the circuitelement is also a function of the frequency at which the circuit isclocked. If the number that is output is the value of a current, thenthe time period of the ALU clock signal will represent a currentmultiplied by time. Therefore the circuit output value is an amount ofcharge or Q.

As an example, a capacitor ALU having a digital value 1, clocked at aclock frequency of 100 MHz will be have a value of C/clock frequency, or10 nanofarads. Hence the actual value of the circuit elements will beset by the clock frequency of the ALU. This feature of the inventionprovides an added advantage in that the band pass frequency of a tunedcircuit configured according to the present invention will change withthe clock frequency. Using this feature of the present invention,applications such as frequency synthesizers and spectrum analyzers canbe easily implemented.

Those of ordinary skill in the art will recognize that resonant circuitsthat have fractionally different resonant frequencies from one anotherwill employ different clock frequencies in the same integrated circuit.It is apparent therefore that care must be taken to guarantee that theALU circuits running at different frequencies will not read input valuesfrom neighboring ALU circuits during data transitions and thus readundetermined values.

One technique to avoid this problem in the circuits configured accordingto the present invention is to make a small FIFO of, for example, threesignal bytes. This would require the use of three ALU circuits, unlessthe ALU circuits are optimized to perform this function. The load signalis determined by the output of one ALU circuit and the dump signal wouldbe determined by the input ALU running at a different frequency. If theFIFO is full, one byte is erased and the next byte loaded. If the FIFOis empty, then the last byte is kept for the next read cycle. This is,of course, only one of many ways to perform this function. Anotherpossible method is to design the ALU circuits with hand shaking suchthat the waiting module will not perform any function on the next clockcycle if the adjacent module is not ready to send or receive the data.

Work has been done in the past in an attempt to design processor arraysto speed up applications. These This class of machines are is calledMIMD or SIMD (multiple instruction multiple data or single instructionmultiple data). The MIMD and SIMD machines do not use interconnect toperform operations such as multiplication and division, and insteadutilize the processor engines to perform these functions in thetraditional manner. Nor do they utilize the concept of varying theprocessor clock frequency to vary the calculation result, as is employedin the present invention. Nor does any of this prior work disclose orsuggest the idea of programming the interconnect to represent an analogfunction to run in real time. Also the processors in these arrays arevery complex and are therefore stuck with subject to the undesirable VonNeuman bottleneck, which is an undesirable characteristic thereofdiscussed above. The architecture of the present invention by its verynature requires each adder/shifter to perform only the one singlefunction so that there is no data bottleneck. This provides constitutesa significant advantage over the prior art.

Another advantage of modeling an analog circuit with an array of addersand shifters with programmable interconnect is that general integerarithmetic can be easily performed by combining adder/shifters. Hencethe end user can design his device to multiply or divide a value by anyinteger when necessary. Since analog circuits typically move a signalalong a circuit path with few feedback terms the additional timerequired for the integer arithmetic may not slow down the circuit asthis architecture will basically pipeline the calculation so long as thecalculation is not in a high speed feedback term.

The architecture of the present invention could be implemented in anFPGA but the modules in these devices are small and designed for logicfunctions, typically one bit wide. Hence many modules would have to beused to make a 10 bit adder and the interconnect architectures in FPGAdevices do not provide a sufficient number of lines to efficientlyimplement the shift function in the interconnect. Hence the circuit costper analog function will be high and the speed will be much slower.Additionally, the modules in an FPGA are not designed to accept signalsarriving asynchronously with the clock signal.

Circuits that utilize feedback that is running at the signal frequency,such as an RLC circuit where the components interact to form a tunedcircuit represent the limiting frequency of the performance of thisinvention. This is caused by a phase shift between the signal and thereaction to that signal which represents at best one clock delay. Forthese applications the circuit will be more stable if the modules areclocked in series rather than in parallel. This of course causes themaximum operating frequency of the circuit to be limited (divided) by afactor of the number of series clock pulse pulses used. Such a clockingscheme is useful for such applications for the Z transform for thespecific circuit to be solved and applied to the module array as opposedto the just placing the circuit elements one to each module.

Two examples of a simple series RLC tuned circuit implemented using thearchitecture of the present invention are shown in FIGS. 11a 11A and 11b11B. Turning first to the embodiment of FIG. 11a 11A the straightforwardplacement requires four ALU modules 130, 132, 134, and 136, driven byfour sequential clocks CLK1, CLK2, CLK3, and CLK4. The circuit isenvisioned as an input node impressed with a voltage V_(in) in serieswith an inductance L in series with a resistance R in series with acapacitance C to ground. ALU module 130, driven by CLK1, computesV_(in)−V_(2prev), where V_(2prev) is the voltage at the node joining theinductance L and resistance R at the last clock cycle. ALU module 132,driven by CLK2, computes i_(prev)+Δi, where i_(prev) is the currentthrough the RLC circuit at the previous clock cycle and Δi is the changein current to the current clock cycle. The current is obtained bydividing the output of ALU module 130 by L (as noted in FIG. 11a 11A).As taught herein, this may be done by the bit shifting techniquedisclosed with reference to FIG. 3 and the accompanying disclosure.

ALU module 134, driven by CLK3, computes V1 _(prev)+i/C, where V1_(prev)V_(1prev) +iC, where V _(1prev) is the voltage at the nodeconnecting the resistance R to the capacitance C at the previous clockcycle and i/C is simply the current i (output of ALU module 132 dividedby the capacitance C (: as noted in FIG. 11a 11A) by the bit shiftingtechnique. ALU module 136, driven by CLK4, computes V1+iR V₁ +iR, whereV1V₁ is the voltage at the node connecting the resistance R to thecapacitance C at the current clock cycle and iR is simply the current i(output of ALU module 132 multiplied by the resistance R (as noted inFIG. 11a 11A) by the bit shifting technique.

As shown in FIG. 11b 11B, judicious placement of the Z transform reducesthe number of clocks to two and increases the number of ALU modules tofive. The implementation of FIG. 11b 11B doubles the maximum frequency.In this sense the present invention can be imagined as a parallelprogrammable Z transform.

In the embodiment of FIG. 11b 11B, the input voltage V_(in) is appliedto ALU module 140, driven by CLK2, which computes X=V_(in-vc)V_(in-Vc),where V_(c) is the voltage across capacitance C in the present cycle.ALU module 142, driven by CLK1, computes the function Y=(X−I_(prev)R)/L,where X is the result of the calculation of ALU module 140, I_(prev) isthe current of the previous cycle, and R and L are the resistance andinductance, respectively. ALU module 144, driven by CLK1, computesZ=I_(prev)−I_(prev)/LC, where L and C are inductance and capacitance,respectively. ALU module 146, driven by CLK2, computes the functionI=Y+Z, where I is the current of the present cycle, and Y and Z are theresults of the last calculations made by ALU modules 142 and 144,respectively. ALU module 148, driven by CLK1, computes V_(c), thevoltage across the capacitance in the present cycle, as V_(cprev), thevoltage across the capacitance C in the previous cycle, minus thequantity I_(prev)/C.

Those of ordinary skill in the art will recognize that The the term IRat one input to ALU module 142 may be obtained by the bit shiftingtechniques taught herein. Similarly, the terms I_(prev)/C Of of ALUmodule 148 and I_(prev)/LC at the input to ALU module 144 may besimilarly obtained. While this bit shifting multiply and dividetechnique does allow use of a minimal number of ALU modules, those ofordinary skill in the art will recognize that the values of themultiplicands and divisors are limited to integers which are powers of2, i.e., 2 . . . 4 . . . 8 . . . 16 2, 4, 8, 16, etc. Such skilledpersons will recognize that divider and multiplier circuits may beconfigured from multiple ALU modules to provide more flexibility ofcomponent value choices at the expense of greater circuit complexity andALU utilization.

Another nice feature of the present invention is that many circuitelements normally employed in analog circuits can be eliminated since nobiasing, impedance matching, or buffering is necessary. A doublebalanced mixer configured using the architecture of the presentinvention requires only one module to perform the function IVC1+V2I/2where ABS(X)is the absolute value of X. The module is programmed to addthe two numbers and if the most significant bit is negative (signedinteger) then perform the two's complement that the module wouldnormally due for a subtract. The divide by two is done on the output tothe interconnect. Hence three coupling transformers, two diodes and anamplifier are modeled by one module.

Variations in gain for circuits such as AGC circuits can be implementedas powers of two by designing the module interconnect with transistorsthat can be switched in the circuit, as opposed to hard wiredinterconnect with antifuses. Another method of varying gain would be toprovide a resistor divider programmed into the modules wherein theresistor value is set in SRAM memory in the module that can be changedon the fly.

Sine wave oscillators are made with this architecture with only twoclocks, one representing the L and one the C. Since these devices aremathematical there is no series resistance and therefore no damping ofthe oscillation. Hence the oscillator, once started, runs forever. Bysetting its initial conditions, the phase and amplitude are determinedfor every cycle until reset. Phase looked loops are therefore simple toimplement. An excellent application would be synchronizing a 3.58 MHzoscillator to the color burst signal of a NTSC (TV) signal for decodingthe color information. The clock frequency will change the oscillatorfrequency and the amplitude can be loaded at any time to synchronizewith the input signal.

As mentioned earlier this technology can combine analog and digitalfunctions with ease. An example would be the combining of a digitalphase locked loop to generate the various clock frequencies required torun the different circuit blocks. This would reduce the need to inputthese signals from off chip and therefore increase speed and reduce pincount and power consumption,

Another feature of this architecture is that once the signal isdigitized a more complex system can be built by merely adding morechips. These would be designed such that all the digital outputs for asignal are adjacent and would match up to the inputs of another chip,allowing communicating pins from chips to be placed side by side. Leadlengths and capacitance loading are therefore minimized, allowingcommunication of the signal from one chip to the next at the maximumpossible frequency. The signal need not be converted back to analoguntil necessary to return the signal to the real world (i.e. speaker orvideo monitor). Of course if the information goes to a computer then thesignal need never be converted back to analog.

The modules may be designed with gated inputs to control the time asignal is loaded as is the case in synchronizing a signal or to steerthe input as is the case with multiplexers.

If desired this architecture could integrate integer divide and multiplyin the modules to perform the calculations thereby eliminating therequirement of using component values of a power of two. Clockfrequencies would not therefore need to be fractionally different. Thisof course would lower the speed and density of the chip but it willstill be considerably faster the than conventional DSP chips as therestill would be no Von Neuman bottleneck.

Some chips could be specialized by designing more specialized modules,optimized for special applications. For example, such a module could beoptimized for the series RLC circuit example disclosed herein and couldspeed up the maximum chip operating frequency by about a factor of two.

From the above description, those of ordinary skill in the art willrecognize that a field programmable version of the architecture of thepresent invention could be used to make prototype circuits, and thatmask programmable versions of the present architecture could be used ina production environment. Such mask programmable versions fall withinthe scope of the present invention.

While embodiments and applications of this invention have been shown anddescribed, it would be apparent to those skilled in the art that manymore modifications than mentioned above are possible without departingfrom the inventive concepts herein. The invention, therefore, is not tobe restricted except in the spirit of the appended claims.

What is claimed is:
 1. A field programmable, digital signal processingintegrated circuit, comprising: a plurality of input/output pads; atleast one analog to digital converter disposed in said integratedcircuit, said at least one analog to digital converter having an analoginput and a plurality of digital outputs; at least one digital to analogconverter disposed in said integrated circuit, said at least one digitalto analog converter having a plurality of digital inputs and an analogoutput; a plurality of ALU (arithmetic logic units) circuits disposed inthe integrated circuit, each of said ALU circuits having a first inputbus for supplying a first n-bit input byte to said ALU circuit on nfirst input lines, a second input bus for supplying a second n-bit inputbyte to said ALU circuit on n second input lines, and an output bus forsupplying an n-bit output byte from said ALU circuit on n output lines;means for individually defining the operation to be performed by each ofsaid ALU circuits; a plurality of interconnect conductors in theintegrated circuit; interconnect means for making programmableconnections between the interconnect conductors, said inputs and outputsof said ALU circuits, said digital inputs and outputs of said at leastone analog to digital converter, said digital inputs and outputs of saidat least one digital to analog converter, and said input/output pads, atleast some of said interconnect means being user programmable; , the noutput lines of at least one of said ALU circuits intersecting ninterconnect conductors to form intersections, said n interconnectconductors connectable to the input lines of other ones of said ALUcircuits; user-programmable interconnect elements disposed at saidintersections; and means for programming ones of said user-programmableinterconnect elements to cause a bit shift of m places in either of theleft and right directions between data on said n output lines of said atleast one of said ALU circuits and said n interconnect conductors,whereby multiplication and division operations may be performed on saiddata by virtue of programmable interconnection.
 2. The fieldprogrammable, digital signal processing integrated circuit of claim 1,further including: at least one PROM circuit disposed in said integratedcircuit, said PROM including a plurality of address input lines and aplurality of data output lines; and interconnect means for connectingselected ones of said interconnect conductors to said plurality ofaddress input lines and said plurality of data output lines of said atleast one PROM circuit.
 3. A field programmable, digital signalprocessing integrated circuit, comprising: a plurality of input/outputpads; at least one analog to digital converter disposed in saidintegrated circuit, said at least one analog to digital converter havingan analog input and a plurality of digital outputs; at least one digitalto analog converter disposed in said integrated circuit, said at leastone digital to analog converter having a plurality of digital inputs andan analog output; a plurality of ALU circuits disposed in the integratedcircuit, each of said ALU circuits having a first input bus forsupplying a first n-bit input byte to said ALU circuit on n first inputlines, a second input bus for supplying a second n-bit input byte tosaid ALU circuit on n second input lines, and an output bus forsupplying an n-bit output byte from said ALU circuit on n output lines;means for individually defining the operation to be performed by each ofsaid ALU circuits; a plurality of interconnect conductors in theintegrated circuit; the n input lines of either of said first and secondinput bus of at least one of said ALU circuits intersecting ninterconnect conductors in sets of ones of said interconnect conductorsconnectable to an output bus of another one of said ALU circuits to formintersections; user-programmable interconnect elements disposed at saidintersections; and means for programming ones of said user-programmableinterconnect elements to cause a bit shift of m places in either of theleft and right directions between data on said n interconnect conductorsand on said n input lines of either of said first and second input busof at said at least one of said ALU circuits and , wherebymultiplication and division operations may be performed on said data byvirtue of interconnection.
 4. A field programmable, digital signalprocessing integrated circuit, comprising: a plurality of input/outputpads; at least one analog to digital converter disposed in saidintegrated circuit, said at least one analog to digital converter havingan analog input and a plurality of digital outputs; at least one digitalto analog converter disposed in said integrated circuit, said at leastone digital to analog converter having a plurality of digital inputs andan analog output; a plurality of ALU circuits disposed in the integratedcircuit, each of said ALU circuits having a first input bus forsupplying a first n-bit input byte to said ALU circuit on n first inputlines, a second input bus for supplying a second n-bit input byte tosaid ALU circuit on n second input lines, and an output bus forsupplying an n-bit output byte from said ALU circuit on n output lines;means for individually defining the operation to be performed by each ofsaid ALU circuits; a plurality of interconnect conductors in theintegrated circuit; interconnect means for making programmableconnections between the interconnect conductors, said inputs and outputsof said ALU circuits, said digital inputs and outputs of said at leastone analog to digital converter, said digital inputs and outputs of saidat least one digital to analog converter, and said input/output pads, atleast some of said interconnect means comprising user-programmableinterconnect elements; said n input lines of the first input bus of atleast one of said ALU circuits intersecting n interconnect conductors infirst sets of ones of said interconnect conductors connectable to anoutput bus of another one of said ALU circuits to form firstintersections; first user-programmable interconnect elements disposed atsaid first intersections; and means for programming ones of said firstuser-programmable interconnect elements to cause a bit shift of m placesin either of the left and right directions between first data on said ninterconnect conductors of said first sets of said interconnectconductors and the n input lines of the first input bus of said at leastone of said ALU circuits, whereby multiplication and division operationsmay be performed on said first data by virtue of interconnection.
 5. Thefield programmable, digital signal processing integrated circuit ofclaim 4, further wherein: said n input lines of the second input bus ofat least one of said ALU circuits intersecting intersect n interconnectconductors in second sets of ones of said interconnect conductorsconnectable to an output bus of another one of said ALU circuits to formsecond intersections; and further comprising: second user-programmableinterconnect elements disposed at said second intersections; and meansfor programming ones of said second user-programmable interconnectelements to cause a bit shift of m places in either of the left andright directions between second data on said n interconnect conductorsof said second set of said interconnect conductors and the n input linesof the second input bus of said at least one of said ALU circuits,whereby multiplication and division operations may be performed on saidsecond data by virtue of interconnection.
 6. A field programmable,digital signal processing integrated circuit, comprising: a plurality ofinput/output pads; a plurality of ALU (arithmetic logic unit) circuitsdisposed in the integrated circuit, each of said ALU circuits having afirst input bus for supplying a first n-bit input byte to said ALUcircuit on n first input lines, a second input bus for supplying asecond n-bit input byte to said ALU circuit on n second input lines, andan output bus for supplying an n-bit output byte from said ALU circuiton n output lines; means for individually defining the operation to beperformed by each of said ALU circuits; a plurality of interconnectconductors in the integrated circuit, said plurality of interconnectconductors forming first sets of intersections with said input busses ofsaid ALU circuits, second sets of intersections with said output bussesof said ALU circuits, and third sets of intersections with input/outputpads, and first ones of said plurality of interconnect conductorsforming fourth sets of intersections with second ones of said pluralityof interconnect conductors, at least some of said first, second, thirdand fourth sets of intersections being programmable by user-programmableinterconnect means; user-programmable interconnect elements at saidintersections of one of said second sets of intersections; and means forprogramming ones of said user-programmable interconnect elements tocause a bit shift of m places in either of the left and right directionsbetween data on said output bus of said one of said ALU circuits andsaid interconnect conductors to perform multiplication and divisionoperations by 2^(m).
 7. A field programmable, digital signal processingintegrated circuit, comprising: a plurality of input/output pads; aplurality of ALU (arithmetic logic unit) circuits disposed in theintegrated circuit, each of said ALU circuits having a first input busfor supplying a first n-bit input byte to said ALU circuit on n firstinput lines, a second input bus for supplying a second n-bit input byteto said ALU circuit on n second input lines, and an output bus forsupplying an n-bit output byte from said ALU circuit on n output lines;means for individually defining the operation to be performed by each ofsaid ALU circuits; a plurality of interconnect conductors in theintegrated circuit, said plurality of interconnect conductors formingfirst sets of intersections with said input busses of said ALU circuits,second sets of intersections with said output busses of said ALUcircuits, and third sets of intersections with input/output pads, andfirst ones of said plurality of interconnect conductors forming fourthsets of intersections with second ones of said plurality of interconnectconductors, at least some of said first, second, third and fourth setsof intersections being programmable by user-programmable interconnectmeans; user-programmable interconnect elements at said intersections ofone of said second sets of intersections; and means for programming onesof said user-programmable interconnect elements to cause a bit shift ofm places in either of the left and right directions between data on saidfirst input bus of said one of said ALU circuits and said interconnectconductors to perform multiplication and division operations by 2^(m).8. A field programmable, digital signal processing integrated circuit,comprising: a plurality of input/output pads; a plurality of ALU(arithmetic logic unit) circuits disposed in the integrated circuit,each of said ALU circuits having a first input bus for supplying a firstn-bit input byte to said ALU circuit on n first input lines, a secondinput bus for supplying a second n-bit input byte to said ALU circuit onn second input lines, and an output bus for supplying an n-bit outputbyte from said ALU circuit on n output lines; means for individuallydefining the operation to be performed by each of said ALU circuits; aplurality of interconnect conductors in the integrated circuit, saidplurality of interconnect conductors forming first sets of intersectionswith said input busses of said ALU circuits, second sets ofintersections with said output busses of said ALU circuits, and thirdsets of intersections with input/output pads, and first ones of saidplurality of interconnect conductors forming fourth sets ofintersections with second ones of said plurality of interconnectconductors, at least some of said first, second, third and fourth setsof intersections being programmable by user-programmable interconnectmeans, wherein one of said first sets of intersections havinguser-programmable interconnect elements at said intersections;user-programmable interconnect elements at said intersections of firstand second ones of first sets of intersections between said input busesof at least one of said ALU circuits and said interconnect conductors;and means for programming ones of said user-programmable interconnectelements to cause a bit shift of m places in either of the left andright directions between data on said first input bus of said one ofsaid ALU circuits and said interconnect conductors to performmultiplication and division operations by 2^(m) , and to cause a bitshift of m places in either of the left and right directions betweendata on said second input bus of said one of said ALU circuits and saidinterconnect conductors to perform multiplication and divisionoperations by 2^(m).
 9. A field programmable, digital signal processingintegrated circuit, comprising: a plurality of input/output pads; aplurality of ALU (arithmetic logic unit) circuit disposed in theintegrated circuit, said at least one ALU circuit having a first inputbus for supplying a first n-bit input byte to a first latch having ninput lines, a second input bus for supplying a second n-bit input byteto a second latch having n input lines, an adder having a first set of ninputs connected to n outputs of said first latch and a second set of ninputs connected to n outputs of said second latch, a third latch havingn inputs connected to n outputs of said adder and n outputs connected toan output bus, and a control circuit having a clock input, an enableinput, an input-ready input, a first control output connected to latchcontrol inputs of said first and second latches, and a second controloutput connected a latch control input of said third latch; and aplurality of interconnect conductors in the integrated circuit, saidplurality of interconnect conductors forming first sets of intersectionswith said input busses of said ALU circuits, second sets ofintersections with said output busses of said ALU circuits, and thirdsets of intersections with input/output pads, and first ones of saidplurality of interconnect conductors forming fourth sets ofintersections with second ones of said plurality of interconnectconductors, at least some of said first, second, third and fourth setsof intersections being programmable by user-programmable interconnectmeans.
 10. The field programmable, digital signal processing integratedcircuit of claim 9, further comprising: a first multiplexer having afirst set of n input lines connected to said first input bus and asecond set of n input lines connected to a third input bus, n outputlines, and a control input connectable to said interconnect conductors;a second multiplexer having a first set of n input lines connected tosaid second input bus and a second set of n input lines connected to afourth input bus, n output lines, and a control input said interconnectconductors; a first inverting circuit having n inputs connected to saidn outputs from said first multiplexer, n outputs connected to said ninput lines of said first latch, and a control input connectable to saidinterconnect conductors; a second inverting circuit having n inputsconnected to said n outputs from said first multiplexer, n outputsconnected to said n input lines of said second latch, and a controlinput connectable to said interconnect conductors.
 11. The fieldprogrammable, digital signal processing integrated circuit of claim 10,wherein said control circuit further includes an input-read output and adata ready output.
 12. The field programmable, digital signal processingintegrated circuit of claim 9, further comprising: user-programmableinterconnect elements at first and second ones of said first sets ofintersections between said first and second input buses of said at leastone of said ALU circuits and said interconnect conductors; and means forprogramming ones of said user-programmable interconnect elements tocause a bit shift of m places between said first input bus of said atleast one of said ALU circuits and said interconnect conductors toperform a division operation by 2^(m) , and to cause a bit shift of mplaces between said second input bus of said at least one of said ALUcircuits and said interconnect conductors to perform a divisionoperation by 2^(m).
 13. The field programmable, digital signalprocessing integrated circuit of claim 9, further comprising:user-programmable interconnect elements at first and second ones of saidfourth sets of intersections, said first input bus of said at least oneALU circuit connectable to said second ones of said interconnectconductors in said first one of said fourth set of intersections, andsaid second input bus of said at least one ALU circuit connectable tosaid second ones of said interconnect conductors in said second one ofsaid fourth set of intersections; and means for programming ones of saiduser-programmable interconnect elements to cause a bit shift of m placesbetween said first ones of said interconnect conductors in said firstone of said fourth set of intersections and said first input bus of saidat least one of said ALU circuits to perform a division operation by2^(m) , and to cause a bit shift of m places between said first ones ofsaid interconnect conductors in said second one of said fourth set ofintersections and said second input bus of said at least one of said ALUcircuits to perform a division operation by 2^(m).
 14. The fieldprogrammable, digital signal processing integrated circuit of claim 9,further comprising: user-programmable interconnect elements at saidsecond set of intersections between said output bus of said at least oneALU circuit and said interconnect conductors; and means for programmingones of said user-programmable interconnect elements to cause a bitshift of m places between said output bus of said at least one of saidALU circuits and said interconnect conductors to perform a divisionoperation by 2^(m).
 15. The field programmable, digital signalprocessing integrated circuit of claim 9, further comprising:user-programmable interconnect elements at one of said fourth sets ofintersections, said output bus of said at least one ALU circuitconnectable to said first ones of said interconnect conductors in saidone of said fourth sets of intersections; and means for programming onesof said user-programmable interconnect elements to cause a bit shift ofm places between said output bus of said at least one of said ALUcircuits and said second ones of said interconnect conductors in saidone of said fourth sets of intersections to perform a division operationby 2^(m).
 16. The field programmable, digital signal processingintegrated circuit of claim 9, further comprising: user-programmableinterconnect elements at first and second ones of said first sets ofintersections between said first and second input buses of said at leastone of said ALU circuits and said interconnect conductors; and means forprogramming ones of said user-programmable interconnect elements tocause a bit shift of m places between said first input bus of said atleast one of said ALU circuits and said interconnect conductors toperform a multiplication operation by 2^(m) , and to cause a bit shiftof m places between said second input bus of said at least one of saidALU circuits and said interconnect conductors to perform amultiplication operation by 2^(m).
 17. The field programmable, digitalsignal processing integrated circuit of claim 9, further comprising:user-programmable interconnect elements at first and second ones of saidfourth sets of intersections, said first input bus of said at least oneALU circuit connectable to said second ones of said interconnectconductors in said first one of said fourth set of intersections, andsaid second input bus of said at least one ALU circuit connectable tosaid second ones of said interconnect conductors in said second one ofsaid fourth set of intersections; and means for programming ones of saiduser-programmable interconnect elements to cause a bit shift of m placesbetween said first ones of said interconnect conductors in said firstone of said fourth set of intersections and said first input bus of saidat least one of said ALU circuits to perform a multiplication operationby 2^(m) , and to cause a bit shift of m places between said first onesof said interconnect conductors in said second one of said fourth set ofintersections and said second input bus of said at least one of said ALUcircuits to perform a multiplication operation by 2^(m).
 18. The fieldprogrammable, digital signal processing integrated circuit of claim 9,further comprising: user-programmable interconnect elements at saidsecond set of intersections between said output bus of said at least oneALU circuit and said interconnect conductors; and means for programmingones of said user-programmable interconnect elements to cause a bitshift of m places between said output bus of said at least one of saidALU circuits and said interconnect conductors to perform amultiplication operation by 2^(m).
 19. The field programmable, digitalsignal processing integrated circuit of claim 9, further comprising:user-programmable interconnect elements at one of said fourth sets ofintersections, said output bus of said at least one ALU circuitconnectable to said first ones of said interconnect conductors in saidone of said fourth sets of intersections; and means for programming onesof said user-programmable interconnect elements to cause a bit shift ofm places between said output bus of said at least one of said ALUcircuits and said second ones of said interconnect conductors in saidone of said fourth sets of intersections to perform a multiplicationoperation by 2^(m).
 20. A field programmable, digital signal processingintegrated circuit, comprising: a plurality of input/output pads; first,second, third and fourth ALU (arithmetic logic unit) circuits disposedin the integrated circuit, each of said ALU circuits having a firstinput bus for supplying a first n-bit input byte to a first latch havingn input lines, a second input bus for supplying a second n-bit inputbyte to a second latch having n input lines, an adder having a first setof n inputs connected to n outputs of said first latch and a second setof n inputs connected to n outputs of said second latch, a third latchhaving n inputs connected to n outputs of said adder and n outputsconnected to an output bus, and a control circuit having a clock input,an enable input, an input-ready input, a first control output connectedto latch control inputs of said first and second latches, and a secondcontrol output connected to a latch control input of said third latch; aplurality of interconnect conductors in the integrated circuit, saidplurality of interconnect conductors forming first sets of intersectionswith said input busses of said ALU circuits, second sets ofintersections with said output busses of said ALU circuits, and thirdsets of intersections with input/output pads, and first ones of saidplurality of interconnect conductors forming fourth sets ofintersections with second ones of said plurality of interconnectconductors, at least some of said first, second, third and fourth setsof intersections being programmable by user-programmable interconnectmeans; said first input bus of said first ALU circuit programmablyconnected to said plurality of interconnect conductors, said secondinput bus of said first ALU circuit programmably connected to saidoutput bus of said second ALU circuit through said plurality ofinterconnect conductors, and said first ALU circuit connected to a clockline by said control circuit in said first ALU circuit; means forcausing a bit shift of m places between said data on said output bus ofsaid second ALU circuit and said second input bus of said first ALUcircuit to perform a division operation by 2^(m); said first input busof said second ALU circuit programmably connected to said output bus ofsaid first ALU circuit through said plurality of interconnectconductors, said second input bus of said second ALU circuitprogrammably connected to said output bus of said third ALU circuitthrough said plurality of interconnect conductors, and said second ALUcircuit connected to said clock line by said control circuit in saidsecond ALU circuit; means for causing a bit shift of j places betweensaid data on said output bus of said first ALU circuit and said firstinput bus of said second ALU circuit to perform a multiplicationoperation by 2^(j); means for causing a bit shift of k places betweensaid data on said output bus of third ALU circuit and said second inputbus of said second ALU circuit to perform a multiplication operation by2^(k); said first input bus of said third ALU circuit programmablyconnected to said output bus of said second ALU circuit through saidplurality of interconnect conductors, said second input bus of saidthird ALU circuit programmably connected to said output bus of saidfourth ALU circuit through said plurality of interconnect conductors,and said third ALU circuit connected to said clock line by said controlcircuit in said third ALU circuit; means for causing a bit shift of mplaces between said data on said output bus of said second ALU circuitand said first input bus of said third ALU circuit to perform a divisionoperation by 2^(m); means for causing a bit shift of h places betweensaid data on said output bus of said fourth ALU circuit and said secondinput bus of said third ALU circuit to perform a multiplicationoperation by 2^(h); said first and second input buses of said fourth ALUcircuit programmably connected to said output bus of said second ALUcircuit through said plurality of interconnect conductors, and saidfourth ALU circuit connected to said clock line by said control circuitin said fourth ALU circuit; and means for causing a bit shift of mplaces between said data on said output bus of said second ALU circuitand said first input bus of said fourth ALU circuit to perform adivision operation by 2^(m).
 21. A field programmable, digital signalprocessing integrated circuit, comprising: a plurality of input/outputpads; first, second, and third ALU (arithmetic logic unit) circuitsdisposed in the integrated circuit, each of said ALU circuits having afirst input bus for supplying a first n-bit input byte to a first latchhaving n input lines, a second input bus for supplying a second n-bitinput byte to a second latch having n input lines, an adder having afirst set of n inputs connected to n outputs of said first latch and asecond set of n inputs connected to n outputs of said second latch, athird latch having n inputs connected to n outputs of said adder and noutputs connected to an output bus, and a control circuit having a clockinput, an enable input, an input-ready input, a first control outputconnected to latch control inputs of said first and second latches, anda second control output connected to a latch control input of said thirdlatch; a memory device disposed in the integrated circuit, said memorydevice having a first n-bit address bus, a second n-bit address bus to asecond latch having n input lines, and an output bus; a plurality ofinterconnect conductors in the integrated circuit, said plurality ofinterconnect conductors forming first sets of intersections with saidinput busses of said ALU circuits, second sets of intersections withsaid output busses of said ALU circuits, and third sets of intersectionswith input/output pads, and first ones of said plurality of interconnectconductors forming fourth sets of intersections with second ones of saidplurality of interconnect conductors, at least some of said first,second, third and fourth sets of intersections being programmable byuser-programmable interconnect means; said first input bus of said firstALU circuit programmably connected to said plurality of interconnectconductors, said second input bus of said first ALU circuit programmablyconnected to said output bus of said second ALU circuit through saidplurality of interconnect conductors, and said first ALU circuitconnected to a clock line by said control circuit in said first ALUcircuit; means for causing a bit shift of m places between said data onsaid output bus of said second ALU circuit and said second input bus ofsaid first ALU circuit to perform a division operation by 2^(m); saidfirst input bus of said second ALU circuit programmably connected tosaid output bus of said first ALU circuit through said plurality ofinterconnect conductors, said second input bus of said second ALUcircuit programmably connected to said output bus of said memory devicethrough said plurality of interconnect conductors, and said second ALUcircuit connected to said clock line by said control circuit in saidsecond ALU circuit; means for causing a bit shift of j places betweensaid data on said output bus of said first ALU circuit and said firstinput bus of said second ALU circuit to perform a multiplicationoperation by 2^(j); said first input bus of said memory deviceprogrammably connected to said output bus of said second ALU circuitthrough said plurality of interconnect conductors, said second input busof said memory device programmably connected to said output bus of saidthird ALU circuit through said plurality of interconnect conductors, andsaid memory device connected to said clock line; means for causing a bitshift of m places between said data on said output bus of said secondALU circuit and said first input bus of said PROM to perform a divisionoperation by 2^(m); means for causing a bit shift of h places betweensaid data on said output bus of said third ALU circuit and said secondinput bus of said PROM to perform a multiplication operation by 2^(h);said first and second input buses of said third ALU circuit programmablyconnected to said output bus of said second ALU circuit through saidplurality of interconnect conductors, and said third ALU circuitconnected to said clock line by said control circuit in said third ALUcircuit; and means for causing a bit shift of m places between said dataon said output bus of said second ALU circuit and said first and secondinput busses of said third ALU circuit to perform a division operationby 2^(m).
 22. A field programmable, digital signal processing integratedcircuit, comprising: a plurality of input/output pads; first, second,third and fourth ALU (arithmetic logic unit) circuits disposed in theintegrated circuit, each of said ALU circuits having a first input busfor supplying a first n-bit input byte to a first latch having n inputlines, a second input bus for supplying a second n-bit input byte to asecond latch having n input lines, an adder having a first set of ninputs connected to n outputs of said first latch and a second set of ninputs connected to n outputs of said second latch, a third latch havingn inputs connected to n outputs of said adder and n outputs connected toan output bus, and a control circuit having a clock input, an enableinput, an input-ready input, an input ready (INR) output, an outputready (OUTR) output, a first control output connected to latch controlinputs of said first and second latches, and a second control outputconnected to a latch control input of said third latch; a plurality ofinterconnect conductors in the integrated circuit, said plurality ofinterconnect conductors forming first sets of intersections with saidinput busses of said ALU circuits, second sets of intersections withsaid output busses of said ALU circuits, and third sets of intersectionswith input/output pads, and first ones of said plurality of interconnectconductors forming fourth sets of intersections with second ones of saidplurality of interconnect conductors, at least some of said first,second, third and fourth sets of intersections being programmable byuser-programmable interconnect means; said first input bus of said firstALU circuit programmably connected to said plurality of interconnectconductors, said second input bus of said first ALU circuit programmablyconnected to said output bus of said second ALU circuit through saidplurality of interconnect conductors, and said first ALU circuitconnected to a clock line by said control circuit in said first ALUcircuit; means for causing a bit shift of m places between said data onsaid output bus of said second ALU circuit and said second input bus ofsaid first ALU circuit to perform a division operation by 2^(m); saidfirst input bus of said second ALU circuit programmably connected tosaid output bus of said first ALU circuit through said plurality ofinterconnect conductors, said second input bus of said second ALUcircuit programmably connected to said output bus of said third ALUcircuit through said plurality of interconnect conductors, and saidsecond ALU circuit connected to said OUTR outputs of said first andthird ALU circuits by said control circuit in said second ALU circuit;means for causing a bit shift of j places between said data on saidoutput bus of said first ALU circuit and said first input bus of saidsecond ALU circuit to perform a multiplication operation by 2^(j); meansfor causing a bit shift of k places between said data on said output busof third ALU circuit and said second input bus of said second ALUcircuit to perform a multiplication operation by 2^(k); said first inputbus of said third ALU circuit programmably connected to said output busof said second ALU circuit through said plurality of interconnectconductors, said second input bus of said third ALU circuit programmablyconnected to said output bus of said fourth ALU circuit through saidplurality of interconnect conductors, and said third ALU circuitconnected to said clock line by said control circuit in said third ALUcircuit; means for causing a bit shift of m places between said data onsaid output bus of said second ALU circuit and said first input bus ofsaid third ALU circuit to perform a division operation by 2^(m); meansfor causing a bit shift of h places between said data on said output busof said fourth ALU circuit and said second input bus of said third ALUcircuit to perform a multiplication operation by 2^(h); said first andsecond input buses of said fourth ALU circuit programmably connected tosaid output bus of said second ALU circuit through said plurality ofinterconnect conductors, and said fourth ALU circuit connected to saidOUTR output of said second ALU circuit by said control circuit in saidfourth ALU circuit; and means for causing a bit shift of m placesbetween said data on said output bus of said second ALU circuit and saidfirst input bus of said fourth ALU circuit to perform a divisionoperation by 2^(m).
 23. A field programmable, digital signal processingintegrated circuit, comprising: a plurality of input/output pads; first,second, third and fourth ALU (arithmetic logic unit) circuits disposedin the integrated circuit, each of said ALU circuits having a firstinput bus for supplying a first n-bit input byte to a first latch havingn input lines, a second input bus for supplying a second n-bit inputbyte to a second latch having n input lines, an adder having a first setof n inputs connected to n outputs of said first latch and a second setof n inputs connected to n outputs of said second latch, a third latchhaving n inputs connected to n outputs of said adder and n outputsconnected to an output bus, and a control circuit having a clock input,an enable input, an input-ready input, a first control output connectedto latch control inputs of said first and second latches, and a secondcontrol output connected to a latch control input of said third latch; aplurality of interconnect conductors in the integrated circuit, saidplurality of interconnect conductors forming first sets of intersectionswith said input busses of said ALU circuits, second sets ofintersections with said output busses of said ALU circuits, and thirdsets of intersections with input/output pads, and first ones of saidplurality of interconnect conductors forming fourth sets ofintersections with second ones of said plurality of interconnectconductors, at least some of said first, second, third and fourth setsof intersections being programmable by user-programmable interconnectmeans; said first input bus of said first ALU circuit programmablyconnected to said plurality of interconnect conductors, said secondinput bus of said first ALU circuit programmably connected to saidoutput bus of said fourth ALU circuit through said plurality ofinterconnect conductors, and said first ALU circuit connected to a firstclock line by said control circuit in said first ALU circuit; said firstinput bus of said second ALU circuit programmably connected to saidoutput bus of said first ALU circuit through said plurality ofinterconnect conductors, said second input bus of said second ALUcircuit programmably connected to said output bus of said second ALUcircuit through said plurality of interconnect conductors, and saidsecond ALU circuit connected to a second clock line by said controlcircuit in said second ALU circuit; means for causing a bit shift of mplaces between said data on said output bus of said first ALU circuitand said first input bus of said second ALU circuit to perform adivision operation by 2^(m); said first input bus of said third ALUcircuit programmably connected to said output bus of said second ALUcircuit through said plurality of interconnect conductors, said secondinput bus of said third ALU circuit programmably connected to saidoutput bus of said third ALU circuit through said plurality ofinterconnect conductors, and said third ALU circuit connected to a thirdclock line by said control circuit in said third ALU circuit; means forcausing a bit shift of j places between said data on said output bus ofsaid second ALU circuit and said first input bus of said third ALUcircuit to perform a division operation by 2^(j); said first input busof said fourth ALU circuit programmably connected to said output bus ofsaid second ALU circuit through said plurality of interconnectconductors, said second input bus of said fourth ALU circuitprogrammably connected to said output bus of said third ALU circuitthrough said plurality of interconnect conductors, and said fourth ALUcircuit connected to a fourth clock line by said control circuit in saidfourth ALU circuit; and means for causing a bit shift of k placesbetween said data on said output bus of said second ALU circuit and saidfirst input bus of said fourth ALU circuit to perform a multiplicationoperation by 2^(k).
 24. A field programmable, digital signal processingintegrated circuit, comprising: a plurality of input/output pads; first,second, third, fourth and fifth ALU (arithmetic logic unit) circuitsdisposed in the integrated circuit, each of said ALU circuits having afirst input bus for supplying a first n-bit input byte to a first latchhaving n input lines, a second input bus for supplying a second n-bitinput byte to a second latch having n input lines, an adder having afirst set of n inputs connected to n outputs of said first latch and asecond set of n inputs connected to n outputs of said second latch, athird latch having n inputs connected to n outputs of said adder and noutputs connected to an output bus, and a control circuit having a clockinput, an enable input, an input-ready input, a first control outputconnected to latch control inputs of said first and second latches, anda second control output connected to a latch control input of said thirdlatch; a plurality of interconnect conductors in the integrated circuit,said plurality of interconnect conductors forming first sets ofintersections with said input busses of said ALU circuits, second setsof intersections with said output busses of said ALU circuits, and thirdsets of intersections with input/output pads, and first ones of saidplurality of interconnect conductors forming fourth sets ofintersections with second ones of said plurality of interconnectconductors, at least some of said first, second, third and fourth setsof intersections being programmable by user-programmable interconnectmeans; said first input bus of said first ALU circuit programmablyconnected to said plurality of interconnect conductors, said secondinput bus of said first ALU circuit programmably connected to saidoutput bus of said fifth ALU circuit through said plurality ofinterconnect conductors, and said first ALU circuit connected to a firstclock line by said control circuit in said first ALU circuit; said firstinput bus of said second ALU circuit programmably connected to saidoutput bus of said first ALU circuit through said plurality ofinterconnect conductors, said second input bus of said second ALUcircuit programmably connected to said output bus of said fourth ALUcircuit through said plurality of interconnect conductors, and saidsecond ALU circuit connected to a second clock line by said controlcircuit in said second ALU circuit; means for causing a bit shift of mplaces between said data on said output bus of said fourth ALU circuitand said second input bus of said second ALU circuit to perform amultiplication operation by 2^(m); said first input bus of said thirdALU circuit programmably connected to said output bus of said fourth ALUcircuit through said plurality of interconnect conductors, said secondinput bus of said third ALU circuit programmably connected to saidoutput bus of said fourth ALU circuit through said plurality ofinterconnect conductors, and said third ALU circuit connected to saidsecond clock line by said control circuit in said third ALU circuit;means for causing a bit shift of j places between said data on saidoutput bus of said fourth ALU circuit and said first input bus of saidthird ALU circuit to perform a division operation by 2^(j); said firstinput bus of said fifth ALU circuit programmably connected to saidplurality of interconnect conductors, said second input bus of saidfifth ALU circuit programmably connected to said output bus of saidfourth ALU circuit through said plurality of interconnect conductors,and said fifth ALU circuit connected to said second clock line by saidcontrol circuit in said fifth ALU circuit; and means for causing a bitshift of k places between said data on said output bus of said fourthALU circuit and said second input bus of said fifth ALU circuit toperform a division operation by 2^(k).